RSTA=0, RSTD=0, DVS=0, PEREN=0, HCKEN=0, IPGEN=0, DTOCV=0000, RSTC=0
System Control register
| IPGEN | IPG Clock Enable 0 (0): Bus clock will be internally gated off. 1 (1): Bus clock will not be automatically gated off. |
| HCKEN | System Clock Enable 0 (0): System clock will be internally gated off. 1 (1): System clock will not be automatically gated off. |
| PEREN | Peripheral Clock Enable 0 (0): SDHC clock will be internally gated off. 1 (1): SDHC clock will not be automatically gated off. |
| SDCLKEN | SD Clock Enable |
| DVS | Divisor 0 (0): Divisor by 1. 1 (1): Divisor by 2. 14 (1110): Divisor by 15. 15 (1111): Divisor by 16. |
| SDCLKFS | SDCLK Frequency Select 1 (1): Base clock divided by 2. 2 (10): Base clock divided by 4. 4 (100): Base clock divided by 8. 8 (1000): Base clock divided by 16. 16 (10000): Base clock divided by 32. 32 (100000): Base clock divided by 64. 64 (1000000): Base clock divided by 128. 128 (10000000): Base clock divided by 256. |
| DTOCV | Data Timeout Counter Value 0 (0000): SDCLK x 2 13 1 (0001): SDCLK x 2 14 14 (1110): SDCLK x 2 27 |
| RSTA | Software Reset For ALL 0 (0): No reset. 1 (1): Reset. |
| RSTC | Software Reset For CMD Line 0 (0): No reset. 1 (1): Reset. |
| RSTD | Software Reset For DAT Line 0 (0): No reset. 1 (1): Reset. |
| INITA | Initialization Active |